The prior art, including the above-identified related application, describes three dimensional RRAM memory arrays having two resistors (2R) per cell, in which two bit lines of a given cell are located in the same plane. The memory resistors are fabricated on top of the two bit lines, while the word line is fabricated on top of the memory resistors. Thus the plan area is relatively large. A disadvantage of the 3-D RRAM of the related application is a large cell size. This disclosure demonstrate a 2-R Cell RRAM array with cell size of 4F2 and a method of making this memory array.